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ASIC Design and Synthesis

- RTL Design Using Verilog

About ASIC Design and Synthesis

This book describes simple to complex ASIC design practical scenarios using Verilog. It also covers architecture design strategies, multiple clock domain designs, low-power design techniques, DFT, pre-layout STA and the overall ASIC design flow with case studies.

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  • Language:
  • English
  • ISBN:
  • 9789813346444
  • Binding:
  • Paperback
  • Pages:
  • 330
  • Published:
  • January 7, 2022
  • Edition:
  • 12021
  • Dimensions:
  • 155x235x0 mm.
  • Weight:
  • 539 g.
Delivery: 1-2 weeks
Expected delivery: December 7, 2024

Description of ASIC Design and Synthesis

This book describes simple to complex ASIC design practical scenarios using Verilog. It also covers architecture design strategies, multiple clock domain designs, low-power design techniques, DFT, pre-layout STA and the overall ASIC design flow with case studies.

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