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Design of Cost-Efficient Interconnect Processing Units
- Spidergon STNoC
part of the System-on-Chip Design and Technologies series
- Binding:
- Hardback
- Pages:
- 288
- Published:
- September 16, 2008
- Dimensions:
- 156x234x25 mm.
- Weight:
- 700 g.
Delivery:
2-3 weeks
Expected delivery: March 22, 2025
Description of Design of Cost-Efficient Interconnect Processing Units
Examines the technology that is set to replace well-known shared bus architectures, such as STBus, for demanding multiprocessor system-on-chip (SoC) applications. This book shows how the System-on-Chip and Network-on-Chip technology works why developers designed it the way they did the system-level design methodology.
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