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Logic Synthesis and Verification Algorithms
- Binding:
- Paperback
- Pages:
- 564
- Published:
- March 17, 2013
- Edition:
- 11996
- Dimensions:
- 178x254x31 mm.
- Weight:
- 1126 g.
Delivery:
1-2 weeks
Expected delivery: January 5, 2025
Extended return policy to January 30, 2025
Description of Logic Synthesis and Verification Algorithms
Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits).
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