Sequential Logic and Verilog HDL Fundamentals

This self-contained tutorial comprehensively discusses the analysis and synthesis of both synchronous and asynchronous sequential machines. These machines are implemented using Verilog Hardware Description Language (HDL), in accordance with the Institute of Electrical and Electronics Engineers (IEEE) Standard: 1364-1995. The book first introduces Verilog HDL and then uses it to design synchronous sequential machines and alternative synchronous sequential machines. Next, the text describes the synthesis of asynchronous sequential machines using Verilog HDL, and provides synthesis examples of pulse-mode asynchronous sequential machines using Verilog HDL.